1. Field of the Invention
The present invention relates to electrically erasable programmable memory cells, and more particularly to such cells as optimized for use in programmable logic devices.
2. Description of Related Art
A typical programmable logic array (PLA), which is a type of programmable logic device, incorporates a plurality of input terms feeding a programmable AND array, the output of which feeds either a fixed or programmable OR array. The output of the OR array may or may not pass through output circuitry before being made available to external package pins. The outputs of the AND array constitute product terms, and the array is programmable to select which of the inputs are ANDed together to form each of the product terms. A typical device which incorporates the above elements is the AmPAL22V10, described in the data sheet therefor published in October 1986. It should be noted that due to the laws of Boolean algebra, any AND array may be viewed equally as an OR array, and vice versa, and either or both in combination may be implemented in other forms in a combinatorial logic array.
Programmable cells for use in programmable logic devices are typically arranged into words, each word representing an input term and each row of cells in corresponding positions in different words representing a product term. Each cell has two states: one in which the input associated with the cell acts on the product term and one in which it does not. All inputs whose cells are programmed to act on a product term are wire-ANDed together to generate the resulting product term signal.
Cells are typically programmable by the user either by burning selected fuses, or by electrically programming a floating gate of a MOS transistor. It has been found particularly advantageous to use floating gate MOS transistors, made programmable and erasable through the use of Fowler-Nordheim tunnelling. The resulting programmable logic device is often called an EEPLD (Electrically Erasable and Programmable Logic Device).
A typical cell for use in an EEPLD is shown in FIG. 1. It includes a floating gate tunnel device 10, and floating gate read transistor 12, and a select transistor 14. The floating gate tunnel device 10 and the floating gate read transistor 12 have a common control gate 16, and a common floating gate 18 located physically beneath the control gate 16. The drain region of the floating gate tunnel device 10 is connected to a node 20, which is also connected to the drain of the floating gate read transistor 12 and to the source of select transistor 14. The source of floating gate read transistor 12 is connected to V.sub.ss, and the source of floating gate tunnel device 10 is left unconnected. Because the capacitive effects of the tunnel devices are so important in these cells, as hereinafter described, the tunnel devices are sometimes referred to herein as "tunnel capacitors".
Floating gate tunnel capacitor 10 includes a tunnel dielectric between the floating gate 18 and the substrate. This tunnel dielectric is made extremely thin in order to permit tunnelling of electrons between the substrate and the floating gate under the influence of the net electric field across the tunnel oxide. It should be noted that though the connected region of floating gate tunnel capacitor 10 is referred to herein as the drain, the interchangeability between drain and source in FET's renders it equally valid to refer to this region as the source of the floating gate tunnel capacitor 10.
When the cell shown in FIG. 1 is placed in an AND array, the drains of all the select transistors 14 in a row are connected together to form a product term (PT). The gates of all the select transistors 14 in a word are connected together to form an input term (IT). In memory technology, product terms become bit lines (BL) and input terms become word lines (WL). Similarly the control gates 16 for all the cells in the AND array are connected to form a word control gate line (CG).
The operation of the cell of FIG. 1 for writing and sensing operations is summarized in the table of FIG. 2. The write mode typically encompasses both a global charging ("programming") step followed by a selective discharge ("selective erasure"). To charge the entire array, the input terms 24 for all words in the array are raised to a voltage greater than the V.sub.T of select transistor 14. This enables conduction between the product term 22 and the nodes 20 in each cell. The control gates 16 for all cells are then raised to a high voltage V.sub.pp, and the product terms 22 are held at ground. V.sub.ss may be left floating or held at ground potential. In this way a net electric field is created across the tunnel dielectric in the floating gate tunnel capacitors and charge is drawn from the drains of the tunnel capacitors to the floating gates.
Selective discharge is typically accomplished one word at a time. First the IT 24 for the selected word is brought to V.sub.pp +V.sub.T and the control gate lines 16 are held at ground. Then only the selected ones of the PT's 22 are brought to V.sub.pp. The high voltage on the input term 24 causes the drain voltage V.sub.d of the tunnel capacitors 10 in the word to track the corresponding PT voltage, so only those cells in the selected word which have V.sub.pp on their PT 22 will have a net electric field tending to discharge electrons from the floating gate to the drain of tunnel capacitor 10. V.sub.ss typically floats during selective discharge.
For words which are unselected during the selective discharge operation, the input term 24 is held at ground to isolate the floating gate tunnel capacitors from product terms 22, which may be at V.sub.pp for discharging other cells connected to the product term. Since the floating gate tunnel device is isolated from the product term line, any voltage on the product term line will not affect the existing charge on the cell (see "don't care" in the table of FIG. 2).
When operating in the read or sense mode, each word is either selected or unselected. If a word is selected (i.e., the input term for that word is high), V.sub.cc is provided to the gate of the select transistor 14. This connects the node 20 to the product term (bit line) 22. The control gate 16 of the cell is held at a read potential V.sub.cg, for example at 1 volt, so that if the common floating gate 18 of the floating gate tunnel capacitor 10 and floating gate read transistor 12 is charged, the read potential is insufficient to overcome the floating gate charge to generate a channel between the source and drain of floating gate read transistor 12. Floating gate read transistor 12 therefore remains off, and the cell has no effect on the voltage of the bit line 22. If the floating gate 18 is discharged, then the read potential is sufficient to generate a channel between the source and drain of floating gate read transistor 12. Assuming V.sub.ss is held at ground potential during the read operation, the bit line 22 will be pulled from its bias potential of V.sub.PT (2 volts, for example) toward ground.
If the cell is unselected (i.e., the input term is at a logic zero level), then the gate of select transistor 14 will be held at 0 volts and the charge stored on the floating gate 18 for the cell will have no effect on the voltage of the product term 22. Thus, in the read mode, only those cells which are connected to the product term 22 and which have discharged floating gates 18 can pull the product term low. Those cells will do so if and only if the input term associated with any one of those cells is high. The product term therefore carries the product of all the input values associated with cells on the product term which have discharged floating gates.
All electrically erasable devices which store charge on a floating gate suffer from potential charge loss over a long period of time due to undesired tunnelling through the tunnel dielectric. Manufacturers usually specify data retention limits at ten (10) years, undesired tunnelling being one of the primary causes of data loss. If the device is unpowered, gradual loss of charge is continuous due to the potential difference between the floating gate 18 and the drain of the floating gate tunnel capacitor 10. If a device is powered, the field across the tunnel dielectric depends in part on the voltage difference between the control gate 16 and drain of floating gate tunnel capacitor 10. In theory this field could be minimized by maintaining an appropriate voltage on the control gate 16. That solution is not satisfactory, however, due to the connection of the drain of floating gate tunnel capacitor 10 to the node 20. The voltage on node 20 changes depending on the voltage level on the product term 22, on the state of charge on the floating gate 10, and on whether or not the cell is selected for read (the state of the input term 24). Since it is not very practical to include circuitry within every cell to adjust the control gate voltage according to all these conditions, typically an intermediate value for V.sub.cg is chosen and gradual charge loss is tolerated.
The problem exists in EEPROMs too, but it is much worse in EEPLDs for two reasons. First, note that read disturb is most severe when a cell is selected since the voltage V.sub.d will typically be at least about one volt above or below V.sub.cg, depending on the product term voltage. This may be tolerable in an EEPROM, since only one cell on each product term (bit line) is selected at a time. In an EEPLD, however, each input term has a corresponding input term. At all times, therefore, about half the cells in the array are selected. The probability that a given cell will be selected at any given time is therefore much greater in an EEPLD, making the potential for read disturb correspondingly greater.
Secondly, the nature of EEPROMs is such that they will be re-programmed much more frequently than will electrically erasable programmable logic devices. Typically EEPROMs are specified for 100 times the number of writes as EEPLDs. Since the data retention period begins anew each time the array is reprogrammed, the data retention period is much less likely to play an important role toward the end of the lifetime specified for an EEPROM than for an EEPLD.
U.S. Pat. No. 4,546,454 to Gupta discloses at FIG. 3 an electrically erasable programmable memory cell circuit for use as an enabling element for a redundant row or column of memory cells in a semiconductor memory array. While the Gupta cell may alleviate some of the problems of other prior art cells, it does not solve them completely. For example, during read mode, there is no access to the control gates of unselected cells since the transistors 214 are turned off. Control of the field across the tunnel dielectric is therefore not permitted when a cell is unselected.
It is therefore an object of the present invention to provide an electrically erasable memory cell which alleviates the above problems.
It is another object of the present invention to provide an electrically erasable programmable cell which minimizes read disturb.
It is another object of the present invention to provide an electrically erasable programmable cell which minimizes the potential across the tunnel dielectric in the worst case during the read mode.
It is another object of the present invention to provide an EEPLD having programmable cells with minimized read disturb.